From: gke0837@tamsun.tamu.edu (Garen Keith Evans) Newsgroups: comp.programming,comp.lang.c Subject: Makefile summary (long) Date: 20 Jan 1994 16:40:42 -0600 Organization: Texas A&M University, College Station (Long:() Hi All, Last year I posted a request for information about make and Makefiles. I received a few responses via email and over the net, as well as a request to summarize and post them to the net. The following is the aforementioned summary. At the end of this summary is another Makefile example, my own. Note: I post this in lieu of a request to do so and also for those folks who may need help with Makefiles. If you already know all there is to know, then there is no sense in continuing:-) Special Thanks to the following people for their help: (Listed in no particular order) Eric Heft Jeff Parker Sting Drew Senko Mark Hahn Jeff Gruszynski Mike Kail Rainer Koch Basile Starynkevitch fox@graphics.cs.nyu.edu rickr@khis.com jtbell@cs1.presby.edu vinson@unagi.cis.upenn.edu barnhoorn@nlev00.nohost.nodomain pho@mserv1.dl.ac.uk The original post: : Hi all, : I have a project with alot of *.c files and a local *.h and would like : to streamline compilation, linking, etc. using a Makefile. : I have looked at other's Makefiles, but they seem pretty cryptic. : And I tried just putting the names of the source files in a file : call 'Makefile' with no result (so now I know it's not THAT easy:-) : Does anyone have suggestions, or a general format they use for : makefiles? : Thanks lots, : Garen gke0837@tamsun.tamu.edu From: eheft@discover.wright.edu (Eric L. Heft) Makefiles aren't too bad if you know: 1) What files you want to compile 2) When each file needs to be compiled Lets start with the following files: list.h list.c ; has #include "list.h" main.c ; has #include "list.h" so, I want to compile list.c then main.c then link list.obj & main.obj into an exe called main. using tcc. #--------------------------------------------------------------------- # MAKEFILE main.exe : list.obj main.obj tcc -ml -eMAIN list.obj main.obj list.obj : list.c list.h tcc -ml -c list.c main.obj : list.h main.c tcc -ml -c main.c # #--------------------------------------------------------------------- line #1 : main.exe : list.obj main.obj says "I need to recompile MAIN.EXE if LIST.OBJ or MAIN.OBJ are out of date, and if I need to recompile MAIN.EXE issue the command 'tcc -ml -eMAIN list.obj main.obj'" line #2 : list.obj : list.c list.h says "I need to recompile LIST.OBJ if LIST.C or LIST.H are out of date, and if I need to recompile LIST.OBJ issue the command 'tcc -ml -c list.c'" line #3 : main.obj : list.h main.c says "I need to recompile MAIN.OBJ if LIST.H or MAIN.C are out of date, and if I need to recompile MAIN.OBJ issue the command 'tcc -ml -c main.c'" ------------------------------------------------------------------- Make will determine is something is 'out of date' by looking at the time/date stamp on the file. so lets say that nothing has been compiled yet and we type 'MAKE' what happens? first make will look for an input file 'makefile', then it starts at the first command/line/reduction ... whatever you want to call the command of the form : ... So from the makefile above , the first command is 'main.exe : list.obj main.obj' So make compares the time/date stamp of MAIN.EXE which doen't exist to LIST.OBJ which doesn't exist , therefor make checks for a command to make LIST.OBJ (found on command #2) make now compairs LIST.OBJ to LIST.C and finds LIST.C is more recent and there are no commands telling what LIST.C is dependent on so it then checks list.h which also has no commands so overall LIST.OBJ needs to be made so make issues the command 'tcc -ml -c list.c' Now , going back up to line #1 , we have resolved LIST.OBJ and make now checks MAIN.OBJ and goes through the same steps ... ------------------------------------------------------------- I like to think of makefile and a tree like : main.exe <---+--- main.obj <---+--- main.c | \--- list.h \--- list.obj <---+--- list.h \--- list.c So to write the depenencies we can see that main.exe depends on main.obj and list.obj or main.exe : main.obj list.obj ------------------------------------------------------------- Now if you understand all that :) you should be able to write the basic makefile. There ARE several other features that make con use to make life easier. you can use MACROS! macros are in the form : LABEL = MACRO DEFINITION and to use the macro in a rule on macro $(LABEL) So we could replace some commonly used part by macros look at the difference between the first and second makefile #--------------------------------------------------------------------- # MAKEFILE main.exe : list.obj main.obj tcc -ml -eMAIN list.obj main.obj list.obj : list.c list.h tcc -ml -c list.c main.obj : list.h main.c tcc -ml -c main.c # #--------------------------------------------------------------------- #--------------------------------------------------------------------- # MAKEFILE CC = tcc MODEL = -ml WARNING = -wpro CFLAGS = $(MODEL) $(WARNING) main.exe : list.obj main.obj $(CC) $(CFLAGS) -eMAIN list.obj main.obj list.obj : list.c list.h $(CC) $(CFLAGS) -c list.c main.obj : list.h main.c $(CC) $(CFLAGS) -c main.c # #--------------------------------------------------------------------- Now if we change from using tcc -> bcc we can change the CC macro and all the files will be compiled using bcc!! the 2nd most used feature is a DEFAULT RULE in which you tell make that any time make needs to build a file of a given type AND there is no give command to issue use the DEFAULT RULE Here you need to check the make you are using as the systax can very but basicly it looks like: .obj.c : $(CC) $(CFLAGS) $!.c where the '.obj.c' says to make a .c -> .obj file issue the command '$(CC) $(CFLAGS) $!.c' where $(CC) -> tcc $(CFLAGS) -> -ml -wpro and $!.c -> goes to the base name of the obj file with a .c ending. So the makefile can be reduced to : #--------------------------------------------------------------------- # MAKEFILE # Macros CC = tcc MODEL = -ml WARNING = -wpro CFLAGS = $(MODEL) $(WARNING) # main target main.exe : list.obj main.obj $(CC) $(CFLAGS) -eMAIN list.obj main.obj # Dependent files list.obj : list.c list.h main.obj : list.h main.c # Default Rules .obj.c : $(CC) $(CFLAGS) $!.c # #--------------------------------------------------------------------- If you have more question , feel free to e-mail me back. I can also send a doc file from a ShareWare make program that I use. Eric =============================================================================== From: mozart@coos.dartmouth.edu (Sting) Well, here's the basic idea for a makefile. Each chunk of the file describes how to build the next layer of the project from its dependencies. For example, let's say we want to build the executable 'foo' from foostuff.h, bar.c, baz.c, bungle.c, yip.c, and gorp.c. THe main program file is foo.c In addition, let's assume that bar.c depends on baz.c and bungle.c. A makefile to do this might contain: --- CC=gcc # set what compiler to use, or it will default to cc foo: bar.o yip.o gorp.o foostuff.h foo.c gcc -O -o foo baz.o bungle.o bar.o: baz.o bungle.o bar.c baz.o: baz.c bungle.o: bungle.c yip.o: yip.c gorp.o: gorp.c --- Make does most of the nasty work of actually setting up the right flags, but if you find it's not doing the right thing, add more customized compiler lines beneath the dependency lines. It's pretty straighforward, in simplest form, although it can be VERY complicated if you want it to do lots of stuff. My recommendation for further ideas is to get the build files for a big program such as emacs or tcsh. There's lots in there to learn from (and that's how I learned after getting started) Good luck! -M -- Michael J. Fromberger Consultant, Postmaster, HD Clinic tech Sting@Dartmouth.EDU / mozart@coos.dartmouth.edu =============================================================================== From: allison@shasta.stanford.edu (Dennis Allison) how about typing man make to look at the man page. A good place to begin. There is also an O'Reilly book on Make which is probably pretty good. =============================================================================== From: mark hahn the basic construct of a makefile is a dependency definition: foo: bar something this defines foo as a goal for which bar must first be satisfied, then something is executed. for instance: foo.o: foo.c cc -c foo.c the implication here is that when foo.c changes, older versions of foo.o are invalidated. now it happens that make has this kind of rule built-in, so all you really need is something like this: CC=gcc CFLAGS=-O2 -static -funroll-functions LDFLAGS=-lm it: foo.o bar.o baz.o $(CC) $(CFLAGS) foo.o bar.o baz.o $(LDFLAGS) -o it foo.o: foo.c shared.h bar.o: bar.c shared.h other.h baz.o: baz.c the whole point of this is that when you type "make", it'll find the first dependency, for "it", figure out if it needs to recompile foo, bar and baz components (based on the last-modified times of the .o files and the .c and .h dependencies. needless to say, there's a lot of other stuff you can do... regards, mark hahn. -- this space intentionally left non-blank. hahn@neurocog.lrdc.pitt.edu =============================================================================== From: mdk@lochness.uhc.com (Mike Kail) Here's a simple Makefile outline, but I suggest that you buy the O'Reilly NutShell book on Make. # # Simple Makefile example # SHELL= /bin/sh CC= cc DEBUG= -g MAXOPT= -O CFLAGS= $(DEBUG) SRC= foo.c bar.c baz.c OBJ= foo.o bar.o baz.o HDRS= myhdr.h WHOAMI= myexecutable # # Targets # help: @echo "Targets are: all, $$WHOAMI, clean, and clobber" all: $(WHOAMI) $(WHOAMI): $(OBJ) $(CC) $(CFLAGS) $(OBJ) -o $@ $(OBJ): $(SRC) $(CC) $(CFLAGS) -c $(SRC) clean: -rm -f $(OBJ) clobber: clean -rm -f $(WHOAMI) -- +---------------------------------------------------------------+ | Mike D. Kail AT&T: (612) 945-6527 | | Advanced Technology, IS&T FAX: (612) 945-6502 | | United HealthCare Corp. E-Mail: mdk@uhc.com | +---------------------------------------------------------------+ | "Nothing great was ever achieved without enthusiasm." | | - Ralph Waldo Emerson | +---------------------------------------------------------------+ =============================================================================== From: Jeff Parker The make format is pretty cryptic, but there is a lot of good features. ORA has a nive book on makefiles. Think of make as a deductive system. You give it dependancies and rules, and it tries to figure out what depends on what. You don't tell me your files, but lets assume main.c depends on util.h and main.h util.c depends on util.h prog is the result of compiling and linking the above Then your file would look like this main.o: main.c util.h main.h cc main.c util.o: util.c util.h cc util.c prog: main.o util.o cc -o prog main.o util.o Gotta run, so I will mail this without checking - good luck - jeff parker - Agile Networks =============================================================================== From: Drew Senko I am assuming that all of your sources are combined to create one executable. I am also assuming that you are not creating a library. Based on these assumptions, the following Makefile *MAY* be what you need. Or at least it's a step in the right direction. You need to know that 'make' has a lot of built-in dependencies. you don't have to specify everything. In fact, for a simply C program, with no header and NO MAKEFILE, you can compile it with 'make' as follows (assume the file is called do_work.c) $ make do_work 'make' will assume that the source file for do_work is do_work.c and will compile it appropriately. I am also assuming you are using unix with the cc compiler. ----- Cut here ----- ## This Makefile relies heavily on built-in 'make' dependencies. Such as: ## - object files are dependent on source files. ## - 'cc' is the compiler. ## The name of the final executable. PROGRAM = executable_name ## The directory containing the local header. LCL_DIR = /users/drew/include ## The source files, followed by the object files. SRCS = src1.c src2.c src3.c src4.c src5.c src6.c src7.c src8.c \ src9.c src10.c src11.c src12.c OBJS = src1.o src2.o src3.o src4.o src5.o src6.o src7.o src8.o \ src9.o src10.o src11.o src12.o ## The local header. HDRS = header.h ## Tell the compiler where header.h is. INCLUDES = -I$(LCL_DIR) ## Any prameters to the C compiler go here (such as -y , -O, etc). CFLAGS = $(INCLUDES) ## ## Create Everything ## - The "all" target should always be the first target. ## all: $(PROGRAM) ## ## Build Program ## ## This says that $(PROGRAM) is dependent on $(OBJS). Therefore, if any .o ## file changes, then $(PROGRAM) should be re-made. $(PROGRAM): $(OBJS) $(CC) -o $(PROGRAM) $(CFLAGS) $(OBJS) ## Note: The $(CC) command above MUST be preceded by a TAB character. ## This says that $(OBJS) is dependent on $(HDRS). Therefore, if any .h ## file [in $(HDRS)] changes, then $(OBJS) should be re-made. $(OBJS): $(HDRS) ----- Cut here ----- To create your executable, try: $ make all OR $ make executable_name 'make' will not re-make a program if it does not think anything has changed. This is why dependencies are so important, and why it is important to get them right. You could simply remove the executable program, but if the .o files still exist, 'make' will only link them, it will not necessarily re-compile them. To force make to re-compile, you could do something like $ touch *.c I would not be surprised if this makefile does not work the first time. I have trouble making them work for me when everything is in front of me. If you try it and it needs some work, e-mail me with the symptoms and I'll try to help. -- Drew Senko drew@eon.com =============================================================================== From: Jeff Gruszynski Get the O'Reilly & Assoc's "Make" book. I usually use the default suffix rules for quick and dirty Makefiles using something like : (No explicit reference to *.[ch] need be used. If want that, get the book. :-) ) ---- Cut Here ---- OBJS= alpha.o beta.o gamma.o CFLAGS= -g -I/usr/local/include LDFLAGS= -g -L/usr/local/lib LIBS= -lm # CC has a default definition myprogam: $(OBJS) # will use implicit compilation rules $(CC) -o $@ $(OBJS) $(LDFLAGS) $(LIBS) ---- Cut Here ---- Jeff -- Jeff Gruszynski Semiconductor Test Equipment Systems Engineer Hewlett-Packard (415) or T 694-3381 Jeff_Gruszynski@hpatc3.desk.hp.com =============================================================================== From: Rainer Koch A simple standard-format will not be useful, since make is like a language-interpreter, but you can construct a simple makefile by using only one of the many available constructs. As you should have read in the man-page a make simplifies compiling (and other) work by making use of rules and dependencies, i.e. the lines routine1.o: routine1.c cc -c routine1.c means: routine1.o depends on the existance of a file routine1.c. In case file routine1.c is newer than routine1.o execute the following, indented line(s). These should then create file routine1.o from routine1.c. By applying those rules to all of your files you can create a simple, but full functional makefile. To link your files use something like: program: routine1.o routine2.o routine_n.o cc -o program routine1.o routine2.o routine_n.o But that's of course not the full functionality of make. Make has the ability to apply one rule to several files by making use of variables or using special (postfix-) rules. One of those special rules is .o.c: $(CC) $(CFLAGS) -c $< This means: for every file NAME.o requested (by naming it in dependencies) look for a file NAME.c, and if it exists and is newer than NAME.o, or NAME.o does not exist, execute the following indented line and substitute the $(CC) and $(CFLAGS) by the contents of the (environment- ?!) variables CC and CFLAGS, as if the shell has done this substitution, and substitute $< by then name of the infile (NAME.c). As you can see rules like my first one are not necessary, since they are covered by this postfix-rule. You only need such lines if you need special options to cc, that can not be passed via CFLAGS due to improper argument- position or when only applying to some of the infiles. For a complete listing of variables and builtin-rule use "make -p" (large !). One hint: use one! for indention, not spaces, some makes get confused on multiple white-space as indention. Hope this helps. -- ___ email: koch@kapp-coburg.de KAPP & Co. / ) / / / Callenberger Str. 52-58 /___/ __ o __ __ __ /__,' __ __ /__ 96450 Coburg, Germany / ) ___) / / ) /__) / ` / ) / ) / ` / ) phone: +49 9561 866826 / / (__/ / / / (__ / / / (__/ (__, / / fax: +49 9561 866803 =============================================================================== From: vinson@unagi.cis.upenn.edu Hi Garen, It would be nice if make man pages gave an example. If you have access to the Unix programming book, written by Kernighan (or Ritchie) it gives some examples of the use of makefiles. Below is a simple example of how I use make on a Unix system. The file called Makefile (with that capitalization) is the default file that make looks for, but you can use any name you like by calling make with the -f filename option. -------------------------- # Makefile for stuff in C directory LIBS= -lm -g OBJS= sample-stiff.o ludcomp.o stiff.o nrutil.o CC= gcc sample: $(OBJS) $(CC) $(OBJS) $(LIBS) -o sample nrutil.o: nrutil.h stiff.o: nrutil.h ludcomp.o: nrutil.h ---------------------------- This Makefile is used to compile some C programs (sample-stiff, ludcomp, stiff, and nrutil). The three first lines set up variables that I use in other places in the program. Variables must be referred to with $(variable) for reasons I don't completely understand. The CC= line sets up which C compiler make will use if I don't tell it otherwise. sample: $(OBJS) $(CC) $(OBJS) $(LIBS) -o sample These two lines set up dependencies and tell make how to build "sample" if I had said "make sample". The first line tells make that "sample" depends upon $(OBJS) which happen to be the object files of the source files. I could just as easily made this a list of source files, but it seems better form to list the object files. The second line tell make how to create the desired file. In this case, I tell it to use gcc to compile the object files with the libraries and call the resulting file "sample". Make first looks to see if sample exists and if it is older than the files it depends upon it will recompile. This is done recursively, so that if the files in $(OBJS) are older than the files they depend on they will be recompiled. The other lines tell make that those object files depend on nrutil.h and make will recompile them if nrutil has changed. Make is also smart enough to know which compiler to use for Fortran, C, and several other languages. Hope this helps a bit. Jack Vinson vinson@unagi.cis.upenn.edu The Purple Puddle Eater and Captain Jack "Skin ain't got no tailored pockets." - Eat _Sell_Me_a_God_ =============================================================================== From: Basile STARYNKEVITCH There are a lot of books on Make. Also GNU make have manual in texinfo format (hence online info files). Several prototypical makes exists. Some program builders are better than make; eg cook, or jam. Basile STARYNKEVITCH ---- Commissariat a l Energie Atomique DRN/DMT/SERMA * C.E. Saclay bat.470 * 91191 GIF/YVETTE CEDEX * France fax: (33) 1- 69.08.23.81; phone: (33) 1- 69.08.40.66 email: basile@soleil.serma.cea.fr; homephone: (33) 1- 46.65.45.53 N.B. Any opinions expressed here are solely mine, and not of my organization. N.B. Les opinions exprimees ici me sont personnelles et n engagent pas le CEA. =============================================================================== And received over the net: From barnhoorn@nlev00.nohost.nodomain Fri Dec 17 13:24:20 CST 1993 Check your compiler-manual for the 'cryptic' options. What a makefile should look like is this: file_to_create: file_it_depends_on how_to_create_that_file You have to add such a line-combination for every file that has to be created. Source-files are files you create yourself, object-files and executables are files that have to be created. So when you have four source files, main.c, main.h, rout1.c, rout2.c, and all *.c files include the file 'main.h', you might consider a makefile that looks like this: main.exe: main.o main.h link main.o+rout1.o+rout2.o to main.exe main.o: main.c main.h cc main.c rout1.o: rout1.c main.h cc rout1.c rout2.o: rout2.c main.h cc rout2.c ('link' and 'cc' are fictive commands that you have to replace with your system-dependent linker and compiler respectively). -- Jaco Barnhoorn barnhoorn%31.40.dnet@se.alcbel.be P.O.Box 63527 2502 JM The Hague 'Doet u het niet voor het geld of de prijzen? Doe het The Netherlands dan voor het milieu!' =============================================================================== From pho@mserv1.dl.ac.uk Fri Dec 17 13:24:58 CST 1993 > Check your compiler-manual for the 'cryptic' ... [Stuff deleted] > system-dependent linker and compiler respectively). You shouldn't need to go that far. There are inbuilt rules to make .o files from .c files and the .h dependencies should be checked automatically. Thus all you would need is something like:- main.exe: main.o rout1.o rout2.o link main.o+rout1.o+rout2.o to main.exe --- Pete Owens P.Owens@nnga.dl.ac.uk =============================================================================== From fox@graphics.cs.nyu.edu Fri Dec 17 13:25:20 CST 1993 ] You shouldn't need to go that far... [Stuff Deleted] ] main.exe This is probably best discovered later on. If makefiles look like complete gibberish you should learn the explicit form first. =============================================================================== From rickr@khis.com Fri Dec 17 13:25:50 CST 1993 First question do you have access to make? If you do then there is a good nut-shell book on the art of makefiles. Those of us that use makefiles never build them from scratch. We all carry around with us a template makefile that we wrote as our first makefile. It would be best if you could write your own makefile from reading about it. There are many different ways to use them and you should understand all the things that are in your makefiles. If all you get is advise and no makefiles and you still want an example, send me e-mail and I will e-mail a makefile. Rick Ratliff | "...if we travel by Objective Software Solutions, Inc. | dragonfly" -- Jimi Hendrix P.O. Box 974, Rowlett, Texas 75030-0974 | (214) 412-5419 | Opinions expressed are mine e-mail: rickr@khis.com | and not those of KHIS. on contract @ Kodak Health Imaging Systems | =============================================================================== From jtbell@cs1.presby.edu Fri Dec 17 13:26:18 CST 1993 Here's another example for you. Actually, it's my own first makefile. I had two programs (ftpsummary and gophersummary) which both used routines in utilities.c. ----------- all : ftpsummary gophersummary ftpsummary : ftpsummary.o utilities.o cc ftpsummary.o utilities.o -o ftpsummary gophersummary : gophersummary.o utilities.o cc gophersummary.o utilities.o -o gophersummary ftpsummary.o : ftpsummary.c utilities.h cc -c ftpsummary.c gophersummary.o : gophersummary.c utilities.h cc -c gophersummary.c utilities.o : utilities.c utilities.h cc -c utilities.c clean : rm *.o ftpsummary gophersummary ---------- When I want to compile just one program, I type either "make gophersummary" or "make ftpsummary". If I want to compile both, I type "make all". If I want to get rid of everything except the source files, I type "make clean". To interpret each entry, read it something like this: ftpsummary : ftpsummary.o utilities.o cc ftpsummary.o utilities.o -o ftpsummary means "If ftpsummary doesn't exist, or if either ftpsummary.o or utilities.o is newer than ftpsummary, perform the indicated command." In this case, if either ftpsummary.o or utilities.o doesn't exist, make looks for an entry for that file and performs it first. As someone has pointed out, make can fill in some "default rules" for you, so this makefile doesn't have to be this long. But I think there's something to be said for doing things the long way the first few times, so you can see exactly what's happening. -- Jon Bell Presbyterian College Dept. of Physics and Computer Science Clinton, South Carolina USA =============================================================================== From carroll@nori.cis.udel.edu Fri Dec 17 13:26:56 CST 1993 Have you ever heard the phrase "RTFM"? It's the perfect solution to your problem, guaranteed to teach you *exactly* how to write a correct makefile, and what all of those funky options that you see in there mean. RTFM = Read The Fucking Manual. -- || Mark Craig Carroll: ||"We the people are getting tired of your lies || CIS Grad, Univ of Delaware || We the people now believe that it's time || PGP key available by finger || We're demanding our rights to the answers || carroll@udel.edu || We elect a precedent to state of mind"-Fish =============================================================================== And Finally... The following is the makefile I needed then and now use, and is provided as yet another example of a makefile. Thanks again to all those who offered sincere help on this subject. # # Makefile for gstat. # CC = gcc LDFLAGS = -lm EXENAME = gss NAME = -o $(EXENAME) CFLAGS = -ansi -pedantic -w # Source and object macros SRC1 = mainstat.c anova.c datastat.c grand.c miscstat.c SRC2 = scheffe.c sumstat.c distrib.c graph.c multipop.c SRC3 = ttest.c contab.c duncan.c regstat.c ztest.c SRC4 = test.c help.c corrstat.c OBJ1 = mainstat.o anova.o datastat.o grand.o miscstat.o OBJ2 = scheffe.o sumstat.o distrib.o graph.o multipop.o OBJ3 = ttest.o contab.o duncan.o regstat.o ztest.o OBJ4 = test.o help.o corrstat.o # SOURCE = $(SRC1) $(SRC2) $(SRC3) $(SRC4) OBJECT = $(OBJ1) $(OBJ2) $(OBJ3) $(OBJ4) # Main local header and file with global variables used # externally by source files. HEADER = stat.h GLOBAL_VARS = miscstat.c DEPEND = $(HEADER) $(GLOBAL_VARS) # #Always remember to start actual commands after a tab #eg., The second of the following two lines is preceded by a tab, not spaces. $(EXENAME): $(OBJECT) $(CC) $(NAME) $(CFLAGS) $(OBJECT) $(LDFLAGS) #Uncomment the following line to remove all object files after compilation. # rm *.o # General dependency format, but will recompile everything if any # file changes! #$(OBJECT):$(SOURCE) $(HEADER) # Dependencies listed alphabetically # All files, except grand.c, will be recompiled if either stat.h, # or miscstat.c change. Miscstat.c will be recompiled if itself, or # stat.h change. Each file will be recompiled if itself changes. anova.o :anova.c $(DEPEND) corrstat.o :corrstat.c $(DEPEND) regstat.c contab.o :contab.c $(DEPEND) datastat.o :datastat.c $(DEPEND) distrib.o :distrib.c $(DEPEND) duncan.o :duncan.c $(DEPEND) grand.o :grand.c graph.o :graph.c $(DEPEND) help.o :help.c $(DEPEND) mainstat.o :mainstat.c $(DEPEND) miscstat.o :miscstat.c $(HEADER) multipop.o :multipop.c $(DEPEND) regstat.o :regstat.c $(DEPEND) scheffe.o :scheffe.c $(DEPEND) sumstat.o :sumstat.c $(DEPEND) test.o :test.c $(DEPEND) ttest.o :ttest.c $(DEPEND) ztest.o :ztest.c $(DEPEND) Garen gke0837@tamsun.tamu.edu =============================== =============================================================================