• What is make?
• Format of a makefile
• Macros
• Suffix Rules
• Where to find out more about make

What is make?

Make is a program that is automates the process of file creation. The most common use of make is in constructing programs; however, it can be used to create other types of programs. This document will concentrate on how to use make to construct programs.

The make program needs information to construct a program. This information is kept in a file called a makefile. By default, make looks for a file named Makefile or makefile in the working directory. The -f switch can be used to have make read a different file.

Format of a makefile

A makefile is a text file that is created using a text editor (e.g., emacs). The # character starts a comment which continues until the end of the line.

The main components of a makefile are dependency lines. A dependency line defines a target file and its dependencies. The dependencies tell make what files are used in the construction of the target file. The general form of a dependency line is:
target : dependency [dependency [ ... ]]
For example:
main.o : main.c lib.h
declares that the main.o file is created from the statements in main.c and lib.h.

Optional command lines may be placed after a dependency line. A command line must start with a tab character. (Make sure you text editor does insert an actual tab and not spaces when the TAB key is hit!) Make will use the command lines to reconstruct the target if necessary. For example:

main.o : main.c lib.h
	cc -c main.c

A target is out of date if any of its dependencies are newer than it is. That is, if any one of the dependency files has been modified since the target was last built, the target is out of date.

Usually a makefile contains several interelated targets. Targets are often dependencies of other targets. By default, make tries to build the first target listed in the file. Make builds a tree of the interelationships between targets as it reads the makefile. When making a target, make starts at the bottom of the dependency tree rebuilding dependencies if neccessary. Here is an example makefile:

# Multi-target makefile

# first target is the executable "prog"
prog : main.o sub.o
	xlc -o prog main.o sub.o

# target: main.o
main.o : main.c sub.h
	xlc -c main.c

# target: sub.o
sub.o : sub.c sub.h
	xlc -c sub.c

If the modification times for the files are:

prog	4:00pm
main.o	2:00pm
sub.o	2:00pm
main.c	5:00pm
sub.c	1:30pm
sub.h	1:00pm

By default make builts the first target specified in the makefile. If a different target is preferred, then the target may be specified on the command line. For example:
make main.o
would only build main.o and not prog.

Macros

Make macros allow one to define text used in many places in the makefile in a single place. For example, one might wish to be able to change the name of the C compiler used quickly. A macro may be used to do this. The following line defines a macro named CC to be equal to xlc.
CC = xlc

To use a macro, its name must be enclosed between a $( and ). Marco names are generally capitalized. Here is the makefile from above, rewritten to use macros.

CC = xlc
CFLAGS = -g

prog : main.o sub.o
	$(CC) $(CFLAGS) -o prog main.o sub.o

# target: main.o
main.o : main.c sub.h
	$(CC) $(CFLAGS) -c main.c

# target: sub.o
sub.o : sub.c sub.h
	$(CC) $(CFLAGS) -c sub.c

The CC and CFLAGS marcos allow the name of the compiler and any complier flags to be easily changed.

Suffix Rules

Make maintains suffix rules that it uses to automate the building of common types of files. Make already has suffix rules for making C and C++ object files. However, the name of the C and C++ compilers may vary from system to system. The suffix rules use macros to allow the compiler name to specified in the makefile. They also allow the flags to the compiler to be specified with a macro. CC and CFLAGS specify the C compiler and its flags, respectively. CXX and CXXFLAGS specify the C++ compiler and its flags.

Suffix rules are used when the command line after a dependency line is empty. Here is yet another version of the above makefile.

CC = xlc
CFLAGS = -g

# still need a command line here!
prog : main.o sub.o
	$(CC) $(CFLAGS) -o prog main.o sub.o

# no command lines needed here!
main.o : main.c sub.h

sub.o : sub.c sub.h

Make predefines many suffix rules, and others can be specified in the makefile. Specifying new suffix rules is beyond the scope of this document.

Where to find out more about make

An excellent source for information about make is the book:
Managing Projects with make by Andrew Oram & Steve Talbott, 2nd Edition
published by O'Reilly & Associates, Inc.

There are also other web pages describing make:

• GNU make
• Another GNU make
• Discussion of how to use make